What Is The Size Of The Smallest Data Item In Main Memory That Has A Memory Address?

Memory

Memories hold one or more $.25 of information:

Information (Integers, Reals, Text)
CPU Instructions (i.east. Estimator programs)
Memory Addresses ("Pointers" to information or instructions)

The contents of a memory remain unchanged unless overwritten with a new chip pattern. For some memories the contents are "lost" when power to the memory is turned off.

Computers employ many different types of retentivity (semi-conductor memory, magnetic disks and tapes, CD-ROMs etc.) to agree information and programs. Each blazon of memory has its own characteristics and uses.

Register Retentivity

Registers are memories located inside the Cardinal Processing Unit (CPU). They are few in number (in that location are rarely more than 64 registers) and as well small in size, typically a register is less than 64 $.25 in size.

The contents of a annals can be �read� or �written� very quickly withal, oft an gild of magnitude faster than chief retention and several orders of magnitude faster than deejay retentiveness.

Different kinds of register are plant within the CPU. General Purpose Registers are bachelor for general use past the programmer. Unless the context implies otherwise we�ll use the term "Register" to refer to a Full general Purpose Register within the CPU. Most mod CPU�s take between 16 and 64 General Purpose Registers. Special Purpose Registers have special uses and are either nonprogrammable and internal to the CPU or accessed with special instructions by the developer.

Examples of such registers include:

Program Counter/Education Arrow Register (PC/IP)
Instruction Annals (IR)
ALU Input & Output Registers
Condition Code (Condition/Flags) Register
Stack Pointer Register (SP)

Although Annals Size (the size of the Register bit-grouping) tends to vary co-ordinate to register type, the Give-and-take Size of an Compages is oftentimes (but not always!) defined by the Size of the General Purpose Registers.

In contrast to Main memory and disk retention, registers are �addressed� directly by specific instructions or past encoding a annals number within a estimator instruction. At the programming (associates) language level of the CPU, registers are commonly specified with special identifiers (e.chiliad. R0, R1, R7, SP, PC)

A final signal, the contents of a register are lost if power to the CPU is turned off, so registers are unsuitable for property long-term information or information that is needed for memory later a power-shutdown or failure. Registers are however, the fastest memories, and if exploited tin issue in programs that execute very quickly.

Principal Retentivity (RAM)

If nosotros were to sum all the bits of all registers inside CPU, the total amount of memory probably would not exceed 5,000 bits. Most computational tasks undertaken past a computer require a lot more retention. Main retentivity is the next fastest retentiveness within a Figurer and is much larger in size.

Typical primary retentivity capacities for unlike kinds of computers are:

Personal Computer	256MB
Fileserver	4GB
Database Mainframe	32GB

Computer Architectures as well impose an architectural constraint on the maximum allowable RAM. This constraint is commonly equal to 2^WordSize memory locations

RAM (Random Access Memory) is the most mutual form of Main Retentivity. RAM is commonly located on the motherboard and then is typically less than 12 inches from the CPU. ROM (Read Only Retention) is like RAM except that its contents cannot be overwritten. ROM retention is often used to shop the �kicking� or starting time-up plan that a figurer executes when powered on.

Although slower than annals retentivity, the contents of whatever location in RAM tin can still be �read� or �written� very speedily. The time to read or write is referred to every bit the access time and is the same for all RAM locations.

In contrast to register retentivity, RAM is used to agree both program code (instructions) and data (numbers, strings etc). Programs that are running are normally �loaded� into RAM from a disk prior to execution by the CPU.

Locations in RAM are identified by an addressing scheme e.g. numbering the bytes in RAM from 0 onwards. The contents of RAM are lost if the power is turned off.

Disk Memory

Disk memory is used to hold programs and data over the longer term. The contents of a disk are Non lost if the ability is turned off. Disk capacities range from 2GB to over twoscore GB (xl × x⁹). Disks are much slower than Register and Main retentiveness, the access-time to data on disk is typically between 5 and xv milliseconds (5 × 10^-three sec), although disks can typically transfer hundreds or thousands of bytes in one go.

Disks tin can be housed internally within a Computer �box� or externally. There are also many kinds of Disk unit, eastward.g: Magnetic Difficult Disks, Floppy Disks (V. Slow), Magneto-Optical CD Roms/Disks, DVDs.

Disk locations are identified by special deejay addressing schemes (e.g. rail and sector numbers).

Summary of Characteristics

Main Retentivity Arrangement

We can imagine Primary Retentivity to be organised every bit a matrix of bits. Each row represents a memory location, typically this is equal to the word size of the architecture, although it tin can be a word multiple (e.g. 2xWordsize) or a partial word (e.g. one-half the wordsize). For simplicity nosotros will assume that data within Main memory tin can merely be read or written a single row (retention location) at a fourth dimension.

For a 96-flake memory we could organise the memory equally 12 × 8 $.25, or eight × 12 $.25 or 6 × sixteen bits, or even equally 96 × 1 bits or 1 × 96 bits. Each row as well has a natural number Accost which is used for selecting the row:

Byte Addressing

Master-memories generally shop and recall rows, which are multi-byte in length (e.thou. 16-bit word = 2 bytes, 32-scrap word = 4 bytes). Almost architectures however, make Main Memory byte-addressable rather than word addressable. In such architectures the CPU and/or the Main Memory hardware is capable of reading/writing any individual byte. Here is an instance of a Master memory with 16-bit retentivity locations. Note how the memory locations (rows) accept even addresses.

Byte Ordering

The bytes within a multi-byte data item can be numbered from Left-to-Right (Big-Endian) or from Correct-to-Left (Trivial-Endian). In the following example, tabular array cells represent bytes, and the cell numbers betoken the address of that byte in Main Retentiveness.

In Big-Endian systems the near significant byte of a multi-byte data item has the everyman address, while the least meaning byte has the highest accost.

In Niggling-Endian systems, the to the lowest degree pregnant byte of a multi-byte data item has the everyman address, while the most significant byte has the highest address. Annotation: an N-character string value is non treated as one big multi-byte value, but rather every bit N unmarried graphic symbol values, i.e. the first character of the cord e'er has the lowest address, the last character has the highest address. This is true for both big-endian and little-endian.

Example: Show the contents of memory at word accost 24 if that word holds the number given by 122E 5F01H in both the big-endian and the little-endian schemes?

Note: By convention, we social club the bytes within a memory word left-to-right for big-endian and right-to-left for petty-endian.

Instance: Evidence the contents of main memory from word accost 24 if those words concord the text JIM SMITH.

The bytes labelled with ? are unknown. They could hold of import data, or they could be don�t care bytes � the interpretation is left upwards to the developer.

Unfortunately calculator systems, in use today are split betwixt those that are big-endian, and those that are little-endian. This leads to problems when a big-endian computer wants to transfer data to a niggling-endian computer. Some recent architectures (e.grand. PowerPC) allow the endian-ness of the compages to be switched programmatically.

Give-and-take Alignment

Although main-memories are generally organised as byte-addressed rows of words and accessed a row at a time, some architectures, allow the CPU to admission whatever give-and-take-sized bit-group regardless of its byte address. We say that accesses that brainstorm on a memory discussion boundary are aligned accesses while accesses that do non begin on word boundaries are unaligned accesses.

Reading an unaligned give-and-take from RAM requires

Reading of adjacent words
Selecting the required bytes from each discussion
Concatenating those bytes together => Irksome

Writing an unaligned give-and-take is even more complex and SLOWER. For this reason some architectures prohibit unaligned word accesses. eastward.g. On the 68000 compages, words must not be accessed starting from an odd-address (e.grand. 1, iii, v, seven etc). Some architectures extend this principle to multi-discussion accesses. e.g. on the SPARC architecture, 64-scrap data items must have a byte address that is a multiple of 8.

RAM Integrated Circuits (Chips)

Then far, we accept looked at the logical organisation of Main Retention. Physically RAM chips tin be organised in a diverseness of ways as well. Here are 3 methods for forming a 256x8 chip main retention.

In the first case, Main retentiveness is built with a single RAM chip. In the second we use two RAM fries, i gives u.s. the most significant 4 bits, the other, the to the lowest degree significant 4 bits. In the tertiary we apply viii RAM chips, each scrap gives the states one scrap - to read an 8 bit retentivity give-and-take, we would accept to access all 8 RAM fries simultaneously and concatenate the bits.

Retentiveness Banks

Main memories are unremarkably bigger than the size of a single RAM chip. Therefore to access a memory discussion the memory hardware has to read a row in several RAM chips simultaneously and then concatenate the returned results from each RAM chip.

The RAM chips that brand up a main-memory system, are unremarkably grouped into banks that are one memory word wide:

Case: Given Chief Memory = 1M × 16 bit (word addressable),

RAM fries = 256K × iv bit

Banking concern size = RAM chips per retentivity word = Width of Memory Word / Width of RAM Chip = 16/4 = iv

18 bits are required to address a RAM chip (since 256K = two¹⁸ = Length of RAM Flake)

A 1M × sixteen bit word-addressed memory requires 20 address bits (since 1M = 2²⁰).

Therefore 2 $.25 (20−18) are needed to select a banking concern.

The Full number of RAM Chips = (1M × 16) / (256K × 4) = xvi

Total number of BANKS = Total number of RAM chips / BANK size = 16/4 = 4

Interleaved Retention

When memory consists of several banks, some address bits will select the bank, and the remaining $.25 will select a row inside the selected bank.

If the bank selection bits are the least significant bits of the memory address the resulting memory is referred to as low-guild interleaved.

If the banking concern pick bits are the virtually meaning bits of the memory address the resulting memory is referred to as high-order interleaved.

Interleaved memory tin yield performance advantages if more than one banking company tin exist read/written at a time:-

For depression-order interleave if the same row in each banking concern can be read
This is an advantage for a single multi-word access of sequential data such as program instructions, or elements in an array of data.
For high-order interleave, if different banks can exist independently accessed by different units.
This is an advantage if the CPU can admission rows in 1 bank while at the aforementioned time an I/O device (hard disk, etc.) tin access different rows in another bank.

Case: Main Memory = 1M × 8bits, RAM chips = 256K × 4bit.

For this memory we crave 4 × 2 = 8 RAM chips.

Each chip requires eighteen address bits (ie. 2^xviii = 256K).

And 1M × 8 $.25 requires xx address $.25 (ie. two^twenty = 1M )

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last updated: 2-Nov-04 Ian Harries <ih@doctor.ic.ac.britain>